Field of the Invention
The present invention relates to an integrated dynamic memory having word lines for selection of memory cells, and bit lines for reading data signals from the memory cells which make contact with the bit lines. The invention also relates to a method for operating such an integrated dynamic memory.
Integrated dynamic memories such as so-called dynamic random access memories (DRAMs), store data information in memory cells having storage capacitors which are each connected via a selection transistor to one of a number of bit lines. Each of the selection transistors are connected to one of the word lines for selection of the memory cells.
One conventional implementation of a DRAM having so-called complementary bit lines provides for the corresponding bit line and the bit line which is complementary to it to be made to assume the same voltage level (for example 1 V) before reading from the memory cells. Depending on the stored charge value, the voltage level on the bit line is changed by reading from a memory cell via the selection transistor. In the situation where, for example, a positive charge (for example a voltage of 2 V) is stored in the memory cell, the voltage level of the connected bit line is raised (for example from 1 V to 1.1 V if the bit line capacitance is higher by a factor of 10 than the memory capacitance of the memory cell) by reading out via the appropriate selection transistor. The voltage difference between the connected bit line and the complementary bit line is now amplified by a read amplifier, for example to a value of 2 V on the bit line and 0 V on the complementary bit line. If the selection transistor is still open, the amplified voltage value of, for example, 2 V is written back to the memory cell once again. This is an important process, since the memory cells slowly lose their charge via so-called leakage currents.
The high packing densities which are normally used nowadays in integrated memories result in the dimensions of the storage capacitors of the memory cells, and hence also their memory capacitance, being relatively low (albeit typically 20 to 40 fF nowadays). In order to achieve a high packing density, a very large number of the memory cells are generally connected to a single bit line by their selection transistors. In consequence, the bit line has a relatively high capacitance (typically 100 to 200 fF). When the storage capacitor charge is read to the connected bit line, this therefore results in only a very small voltage change of, for example, 50 to 100 mV. The voltage change must be amplified by the read amplifier to a voltage level that is acceptable for reading out and which is, for example, 2 V.
The increasing integration density is making it ever more difficult to produce memory cells with the memory capacitance that is normal nowadays. Since the read amplifiers for the memory occupy a relatively large area, there is, on the other hand, an aim to connect as many memory cells as possible to a single bit line. The capacitance of the bit lines is thus comparably very high, for which reason the voltage changes of the respective bit line as a result of reading from a memory cell are only very small. This in turn results in comparatively slow and complex read amplifiers.
It is accordingly an object of the invention to provide an integrated dynamic memory, as well as a method for operating the integrated dynamic memory which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which allows fast and reliable amplification of data signals to be read from the memory cells, even when the memory cell integration density is high. With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated dynamic memory. The memory contains bit lines, word lines, and a memory cell array having memory cells connected to the word lines for selecting the memory cells and to the bit lines for reading data signals from the memory cells. At least one global bit line runs through the memory cell array but does not make direct contact with the memory cells. A voltage amplifier is connected to one of the bit lines for amplification of a data signal of a respective memory cell, to be read from, to a first voltage level not sufficient for writing the data signal back to the respective memory cell read from. The voltage amplifier is further connected to the global bit line and outputs the data signal amplified to the first voltage level. A read amplifier is connected to the global bit line. The read amplifier amplifies the data signal from the respective memory cell read from to a second voltage level, the second voltage level being sufficient for writing the data signal back to the respective memory cell.
In addition to the bit lines, the integrated dynamic memory according to the invention has at least one global bit line, which is disposed in the memory cell array in the same sense as the bit lines, but does not make direct contact with the memory cells. It is provided, for example, instead of a complementary bit line. Furthermore, a voltage amplifier is provided, which is connected to one of the bit lines for amplification of a data signal from a memory cell, which is to be read from, to a first voltage level, although this is not sufficient for writing the data signal back to the memory cell. The voltage amplifier is furthermore connected to the global bit line in order to output the amplified data signal which is itself connected to a read amplifier for amplification of the data signal which is to be read out, to a second voltage level which, in contrast to the first voltage level, is sufficient for writing the data signal back to the memory cell.
The invention thus provides a hierarchical amplification concept, in which the voltage amplifier acts as a preamplifier. This may be based on a simple circuit principle and, in this case, occupies only a small area on the chip. This makes it possible to shorten the bit lines, and to connect fewer memory cells to the respective bit line. This in turn leads to better voltage signals on the bit line that is to be read out, due to a reduced bit line capacitance. The voltage amplifier, whose configuration may be simple, amplifies the voltage signal on the bit line that is to be read out, and passes this to the global bit line. However, the preamplified signal is not strong enough to write a complete voltage level back to the memory cell which is to be read from. Nonetheless, the preamplified signal is strong enough to cause a considerable voltage change on a long global bit line. This signal can now be amplified via a conventional read amplifier to a full voltage level, which is sufficient for writing back to the memory cell which is to be read from.
During operation of the integrated dynamic memory according to the invention, the bit line that is to be read out and the global bit line are made to assume the same voltage level at the start of a reading-out process. The memory cell that is to be read from is then read from, so that the connected bit line experiences a voltage change. The voltage amplifier is then activated, so that the global bit line assumes the first voltage level, and a preamplified data signal is produced. The read amplifier is then activated, so that the global bit line assumes the second voltage level and hence assumes a value that is suitable for writing back to the memory cell. In order to write the data signal back following the reading-out process, the selected bit line is made to assume the same voltage level as the global bit line, for example via the voltage amplifier. The voltage value is written back to the selected memory cell, which is still open from the previous reading-out process and is selected for writing back the data signal.
The hierarchical amplification concept according to the invention on the one hand requires numerous voltage amplifiers, which act as preamplifiers, in order to provide a memory. On the other hand, the voltage amplifiers may be configured such that they have a relatively small area, since they may be based on a comparatively simple circuit concept. However, the preamplification allows long global bit lines to be driven. Therefore, a comparatively large number of voltage preamplifiers may be connected to one global bit line, so that only a small-number of conventional read amplifiers, which occupy a large area, are now required.
The hierarchical amplification concept according to the invention results in that there is no need to provide complementary bit lines. The global bit line may thus be disposed instead of a complementary bit line, together with the normal bit lines, in the same metallization plane in the memory. This advantageously results in that there is no need for any production processes that are more complicated than those for conventional memories.
In accordance with an added feature of the invention, the voltage amplifier has a connection for an activation signal and a first switch with a controlled path connected between the global bit line and the connection for the activation signal. The first switch has a control connection coupled to one of the bit lines.
In accordance with an additional feature of the invention, the voltage amplifier has a second switch connected to one of the bit lines. The control connection of the first switch is coupled through the second switch to one of the bit lines. The voltage amplifier has a third switch connected to a further one of the bit lines, and the first switch is coupled through the third switch to the further one of the bit lines.
In accordance with another feature of the invention, the voltage amplifier has a fourth switch with a controlled path, and one of the bit lines and the global bit line are connected to each other through the controlled path of the fourth switch.
In accordance with a further feature of the invention, a number of the bit lines are each connected through the voltage amplifier to the global bit line, and the bit lines and the global bit line have different lengths.
In accordance with another added feature of the invention, a metallization plane is provided, and the bit lines and the global bit line are disposed in the metallization plane.
In accordance with another additional feature of the invention, the memory cells have a selection transistor and a memory capacitance. The memory capacitance is in each case connected through the selection transistor to a respective bit line. The selection transistor in each case has a control connection connected to a respective word line. The selection transistors have active areas and the bit lines are disposed such that the active areas of the selection transistors run in parallel with, but in an opposite direction to, the bit lines.
In accordance with a concomitant feature of the invention, the word lines and the active areas of the selection transistors in the memory cells are disposed in an orthogonal grid, and the bit lines run diagonally across the orthogonal grid in a first direction and in a second direction. Each of the bit lines makes contact with a respective memory cell at a point at which the respective bit line changes direction.
In accordance with an added mode of the invention, there is the step of setting the bit line to assume a same voltage level as the global bit line, and the memory cell that was read from is selected for writing back a data signal.
In accordance with a further mode of the invention, there is the step of writing back an inverted signal to the memory cell, and reading out the data signal written back once again in inverted form during a subsequent reading-out process.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated dynamic memory, as well as a method for operating the integrated dynamic memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.